1. Technical Field
The present invention relates to a Built-in Self Test (BIST) system used in a Field Programmable Gate Array (FPGA). More particularly, the present invention relates to providing a BIST in an FPGA that provides for partial reconfiguration.
2. Related Art
As integrated circuit (IC) devices continue to increase in complexity, it is increasingly difficult to test the devices. In particular, in order to test an IC, a large number of test patterns and configurations may be required. The response to the test patterns is then monitored to determine if defects are present. This testing is time-consuming and may use all of the input/output pins of the integrated circuit. Accordingly, it is known to provide one or more circuits in the IC itself to provide a Built-In Self Test (BIST) system.
One type of IC that is becoming increasingly more complex, and thus typically includes a BIST system is a FPGA. FPGAs are programmable or customizable versions of Application Specific Integrated Circuits (ASICs). As opposed to ASICs, programmability enables FPGAs to be purchased by customers and configured to provide a desired circuit.
A large portion of test time for an FPGA is spent configuring or programming the part. Some FPGAs provide for partial reconfiguration to provide for more rapid reprogramming after startup. With partial reconfiguration, portions of the FPGA are reprogrammed, while the remaining portions remain configured without reprogramming. In some cases, partial reconfiguration allows the FPGA to continue operation during the partial reprogramming since certain modules within the FPGA that are not reprogrammed can continue functioning.
A block diagram of components of a conventional FPGA is shown in FIG. 1. The FPGA includes input/output (I/O) blocks 2 (each labeled IO) located around the perimeter of the FPGA, multi-gigabit transceivers (MGT) 4 interspersed with the I/O blocks 2, configurable logic blocks 6 (each labeled CLB) arranged in an array, block random access memory 8 (each labeled BRAM) interspersed with the CLBs, configuration logic 12, configuration interface 14, on-chip processor 16 and an internal configuration access port (ICAP) 20. The FPGA also includes other elements, such as a programmable interconnect structure and a configuration memory array, which are not illustrated in FIG. 1. Although FIG. 1 shows a relatively small number of I/O blocks 2, CLBs 6 and block RAMs 8 for illustration purposes, it is understood that an FPGA typically includes many more of these elements.
In general, the FPGA of FIG. 1 is configured in response to a set of configuration data values that are loaded into a configuration memory array of the FPGA from an external store via configuration interface 14 and configuration logic 12. Configuration interface 14 can be, for example, a parallel select map interface, a JTAG interface, or a master-serial interface. The configuration memory array can be visualized as a rectangular array of bits. The bits are grouped into frames that are one-bit wide words that extend in columns from the top of the array to the bottom. The configuration data values are typically loaded into the configuration memory array one frame at a time from the external store via the configuration interface 14.
The FPGA can be reconfigured by rewriting data in the configuration memory array. In one reconfiguration method, the ICAP 20 is used to rewrite data in the configuration memory array in order to generate or instantiate the FPGA's internal logic (e.g., CLB's 6 and BRAMs 8). In other words, one part of the configured FPGA can reconfigure another part of the FPGA. Without using the ICAP, reconfiguration can also be performed by loading reconfiguration frames through the configuration interface 14 using external customized logic components to over-write frame data in the configuration memory array.
More efficient reconfiguration of an FPGA is performed by only rewriting a portion of the frames or columns in the configuration memory array using partial reconfiguration. One way to enable an FPGA to take advantage of partial reconfiguration is to have the FPGA partitioned into physically separate modules. Each module provides circuit resources for implementing a task, i.e. an algorithm. More complex modules are sometimes termed as Intellectual Property (IP) cores. As the processing requirements change, one or more of the modules are updated only to a degree necessary to perform a new algorithm. Similarly, smaller manipulations of a module can be made such as a change in inputs and outputs. Because modifications to the algorithms performed by a module typically require modification of only a portion of the frames in the configuration memory, efficient operation can result using partial reconfiguration.
In order to provide for efficient partial reconfiguration, a circuit arrangement shown in FIG. 2 is provided. To control reading and writing of data into the configuration memory array 30 of an FPGA, a controller 32 is used. The controller 32 can be included with the ICAP 20 internal to the FPGA. For externally controlled reconfiguration, the controller 32 can also be provided outside the FPGA. To mirror data in the configuration memory array 30, configuration store 34 is used, enabling faster data reading and writing. The configuration store 34 speeds read and write operations because a bottleneck is otherwise created through the configuration interface 14 to the configuration memory array 30. With the configuration store 34 used, data is first modified in the configuration store 34 and later loaded into the configuration memory array 30 through the configuration interface 14 in a frame-by-frame manner.
In a further embodiment for partial reconfiguration, the modification store 36 is added. The modification store 36 includes information identifying physical resources to be modified and the state to which they will be modified. As opposed to the configuration store 34, the controller 32 can read and modify portions of frames in the configuration store 34 using the modification store 36 as a reference, rather than being required to modify entire frames significantly reducing modification time.
With FPGAs providing partial reconfiguration, it is desirable to have a BIST system that can adapt to the partial changes to continue to provide for self testing of all possible signal patterns provided within the FPGA after components have been partially reconfigured.
It is further desirable to have a BIST system that can take advantage of partial reconfiguration of a system to reduce overall test time, as compared to full reconfiguration that would otherwise consume substantial test time while reconfiguring.